Category: Uncategorized

  • uvm_reg_frontdoor – Register access for more complex frontdoors

    In UVM there are two ways of connecting the register model to UVM agents that operate on the design under test. One is using the register adapter, uvm_reg_adapter. What that class does is to convert from a register model sequence item to a sequence item that can be used by our UVM agent’s sequencer. That…

  • Verification planing: Functional checks and coverage.

    How to understand the difference and what it means for verification planning. If I where to explain what it means to be an engineer in the most general terms, I would say that it is to translate a conceptual idea into a practical solution. All of us that have worked as one know that this…

  • 100% Coverage – What does that really mean?

    As digital designers, we always want our design to be perfect when we delivered them. Without any bugs or other mistakes that can cause the device it is integrated in to malfunction. With the sizes and complexity of the designs developed these days, it is clear that it is unrealistic for a a person, or…